After upgrade to 7.11 VDA, Black/Blank screen appears on the monitors while connecting to ICA session.

Complete the following procedure:

  1. Check for the current “System Video Memory” allocation located in the Control Panel,Display,Advanced Settings:

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2. Calculate the video memory that is required for monitors using the following formula:

Note: This formula is specific to VDA version 7.11. SumOfAllMons (Width * Height) * 4 / 0.3, where width and height are resolution of the monitor.

For VDA 7.9 and earlier, refer http://support.citrix.com/article/CTX200257

Example: Consider the resolution of monitor 1 is 1920*1200 and monitor 2 is 1366*768.

Then SumOfAllMons will be (1920*1200 + 1366*768).

Note: There is no hard and fast rule that will work for all cases as composited desktops have random overhead in video memory so we have to allocate additional memory for this overhead.

To get a visualization of the video memory required and size up the MaxVideoMemoryBytes for your specific environment, download sysinternals process explorer and observe the GPU Dedicated Memory graph (View > System Information, or Ctrl+I >GPU tab) inside an active Citrix connection:

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3. Open the registry (regedit) and navigate to:

HKEY_LOCAL_MACHINESYSTEMCurrentControlSetservicesvbdenum

4. Increase the value of “MaxVideoMemoryBytes” REG_DWORD value to the above calculated memory.



5. Reboot the VDA.

Note: The MaxVideoMemoryBytes key(s) should only be used in conjunction with the “Citrix Systems – WDDM Display Driver”. If the “Citrix Display Only Adapter” is in use then these keys should not be set as memory is allocated dynamically.

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Ex-Huawei team design chip to speed up Hyperledger Fabric blockchain

Yesterday Accelor came out of stealth mode to reveal it has designed a new chip to speed up the Hyperledger Fabric blockchain and provide additional security. The company claims that with its chips it’s possible to achieve 200,000 transactions per second. The announcement mentioned the founders are a team of industry heavyweights from Qualcomm, Nvidia and AMD. Their résumés are impressive, but the statement omitted the fact that all three founders left Huawei in July 2018 to found Accelor.

It’s a sensitive issue given the controversial claims made about Huawei by the FBI.

The San Fransisco company also announced $2 million in seed backing from Chengwei Capital, which usually focuses on the Chinese market.

The need

Bitcoin miners have used “ASICS” chips for a few years, with specialist hardware built by companies such as Bitmain and Bitfury. ASICS stands for Application-specific integrated circuit, and every blockchain has distinct characteristics. Doubtless, this was the spark for the idea to create new chip designs targeted at Hyperledger Fabric. However, the Accelor chips don’t appear to be ASICS. They’re FPGA which carry some risks. We’ll come back to that.

“Blockchain has introduced valuable new techniques for how we share and secure private data, but the industry’s software has run up against an impossible triangle between decentralization, security, and performance,” said GJ Chu, Co-founder, Accelor.

“Blockchain applications currently operate on top of retrofitted legacy hardware that relies on a ‘security by patch’ process and is unsuited to the rigorous computation demanded by decentralized protocols. Commodity CPUs are not friendly to the cryptographic, network, and database operations necessary for these systems to scale without sacrificing security and it is paramount for the industry to move these intensive computing functions onto dedicated hardware.”

The solution

Accelor has two aspects to its design. The Accelor Performance Engine (APE) is the part that speeds up the cryptography and other processes to deliver 10x greater throughput compared to software-only solutions.

Additionally, the Accelor Security Architecture (ASA) aims to address current security issues. In the past few years there have been some serious CPU-based vulnerabilities – Spectre, Meltdown, and Foreshadow – which have meant that data that should not be accessible within the CPU potentially could be snooped. The operating system companies have introduced patches to protect users. Accelor asserts that these issues have impacted Trusted Execution Environments, a ring-fenced part of processors, which are usually used to protect cryptographic keys.

The risk

The Accelor statement says that “ASA leverages an FPGA-based confidential computing model that gives users ultimate authority over their hardware, affording each individual the flexibility to choose where to place their root of trust, thereby achieving a more decentralized hardware solution.”

An FPGA is a field-programmable gate array, which means that users can reprogram the circuits. The U.S. Department of Defense states that the “Programmable nature of FPGAs and System on Chips (SOCs) make them vulnerable to cyber malware and malicious insertion.” Others have outlined the security issues here and here. This compares to ASICS which are usually mass produced with the code permanently written to the chip to make them harder to tamper with. And ASICS are much faster than FPGAs.

The benefits

In Accelor’s press announcement, Dr. Larry Shi outlined the benefits of the chips. He’s the Head of the Blockchain Research Team at the University of Houston (UH), and Senior Member of the Institute of Electrical and Electronics Engineers (IEEE).

“Accelor’s confidential computing architecture has three key advantages to deliver a higher standard in trusted computing. Clients have more freedom to manage their devices, such as setting up their own identity management systems to authenticate each device under their control,” he said.

“FPGAs are faster and have greater power efficiency than general purpose processors for computationally intensive tasks such as expensive zero-knowledge proof related operations. Lastly, FPGAs are already widely used in the IoT and embedded systems market.”


Image Copyright: Rost-9 / BigStock Photo

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FPGAs vs. GPUs: A Tale of Two Accelerators

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In deep learning applications, FPGA accelerators offer unique advantages for certain use cases. In artificial intelligence applications, including machine learning and deep learning, speed is everything. Whether you’re talking about autonomous driving, real-time stock trading or online searches, faster results equate to better results. This need for speed has led to a growing debate on the best accelerators for use in AI applications. In many cases, this debate comes down to a question of server FPGAs vs. GPUs — or field programmable gate arrays vs. graphics processing units. To see signs of this lively debate, you … READ MORE



ENCLOSURE:https://blog.dellemc.com/uploads/2019/01/2-Cities-600×356.jpg

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New Dell UltraSharp Monitors Built to Foster Better Workdays, More Loyal Workers

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Anyone who’s worked in an office knows the role an individual’s workspace can play in the course of their day. Just as a squeaky chair or sticky keyboard can make every day a subtle nightmare, a clean, optimized workspace puts people in the headspace to achieve stress-free productivity and deliver better customer experiences. And it’s hard to think of a workspace fixture that has a bigger effect on productivity than the monitor. Forrester 1 has found that visually appealing, productivity-enabling monitors are becoming key for attracting and retaining the best talent, especially as demographics shift toward a … READ MORE



ENCLOSURE:https://blog.dell.com/uploads/2018/10/ultra-sharp2-600×356.png

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Re: Fail safe network in Unity

Wanted to check if this second fail safe network configuration is possible in below case

We have two I/O modules 4 port on SPA and 4 Port on SPB

Ports 0 and 2 are connected to Switch A from SPA and SPB

Ports 1 and 3 are connected to Switch B from SPA and SPB

LACP config

LACP1 —> 2 ports SPA0 SPA2

LACP2 —> 2 Ports SPB0 SPB2

LACP3–>2 ports on SP1 SPA 3

LACP4 —> 2 ports SPB1 SPB 3

In below article found this line .

https://www.emc.com/collateral/white-papers/h15162-emc-unity-high-availability.pdf

“When configuring FSN, ensure the same ports are cabled on both SPs. This is necessary because in case of SP failover, the peer SP uses the same ports. If the cabling does not match, communication issues may occur.” Wanted to know if Fail safe FSN1 with LACP2 and LACP4 would work

Failsafe config

Lets say FSNO —-LACP1 and LACP3 . Can we create Failsafe say FSN1 another one for LACP2 and LACP4 ?

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